(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to integrate the formation of composite insulator spacers on the sides of gate structures of complimentary metal oxide semiconductor (CMOS), devices.
(2) Description of Prior Art
The ability to fabricate CMOS devices comprised of both N channel (NMOS), and P channel (PMOS), devices, on the sane semiconductor chip, requires shared process steps and sequences in order to minimize process complexity as well as processing costs. A specific process sequence, the formation of insulator spacers on the sides of gate structures, can sometimes be shared resulting in identical insulator, or composite insulator spacers, residing on the sides of both NMOS and PMOS gate structures. However to optimize specific device parameters such as minimized series resistance for NMOS devices, as well as reduced risk of short channel effects for PMOS devices, innovations to a global composite insulator spacer process have to be achieved.
This invention will describe a process sequence for formation of a composite insulator spacer on the sides of CMOS gate structures, in which PMOS short channel effects are minimized via source/drain implantation using a composite insulator spacer as a mask, while series resistance for the NMOS device is minimized via source/drain implantation using a thinned composite insulator spacer as a mask. This invention will also feature reductions in the level of isolation field removed during this unique process sequence used to form CMOS spacers. Prior art, such as Pradeep et al, in U.S. Pat. No. 6,277,683B1, describe a process for forming composite spacers on the sides of CMOS devices, however that prior art does not feature the unique process sequence described in this present invention in which an initial composite insulator spacer is used as an implant mask during PMOS source/drain formation, while a final composite insulator spacer is used an implant mask during NMOS source/drain formation.
It is an object of this invention to integrate the fabrication of CMOS devices, comprised of PMOS and NMOS devices, on the same semiconductor chip.
It is another object of this invention to use a composite insulator spacer to define an implanted source/drain region for the PMOS device, while using a partially etched, L-shaped composite insulator spacer to define an implanted source/drain region for the NMOS device.
It is still another object of this invention to remove a doped oxide component of an initial composite insulator spacer, comprised of an underlying silicon oxide shape, a silicon nitride shape, and the overlying doped oxide component, to form the L shaped composite insulator spacer used for definition of the NMOS source/drain region.
In accordance with the present invention a process for integrating the fabrication of NMOS and PMOS devices, featuring a composite insulator spacer used to define an implanted PMOS source/drain region, and featuring a partially etched, L-shaped composite insulator spacer used to define an implanted NMOS source/drain region, is described. After formation of insulator filled, shallow trench isolation (STI), regions, an N well region is formed in a portion of a P type semiconductor substrate to be used for PMOS devices, while the remaining portion of the P type semiconductor substrate, is reserved for accommodation of the subsequent NMOS devices. After formation of gate structures, on an underlying gate insulator layer, N type lightly doped source/drain (LDD), regions, or source/drain extension (SDE) regions, are formed in areas of the P type semiconductor substrate not covered by gate structures, while P type LDD or SDE regions are formed in areas of the N well region not covered by gate structures. A composite insulator layer, comprised of an underlying silicon oxide layer, a silicon nitride layer, and an overlying phosphosilicate glass (PSG), layer, is next deposited. Anisotropic reactive ion etching (RIE) procedures are then employed to define composite insulator spacers, each comprised of an underlying silicon oxide shape, a silicon nitride shape, and a PSG shape, on the sides of all gate structures. The composite insulator spacer is then used for definition of a heavily doped P type source/drain region, via implantation of P type ions in a area of the N well region not covered by a gate structure or by the composite insulator spacer. A photoresist shape protected NMOS regions from this implantation procedure. After removal of the photoresist shape the PSG components of the composite insulator spacers are removed resulting in L-shaped composite insulator spacers, each comprised of an underlying silicon oxide shape and an overlying silicon nitride shape. Another photoresist shape is next used to protect PMOS regions from another ion implantation procedure, used to form a deep, heavily doped N type source/drain region in an area of the P type semiconductor substrate not covered by the gate structure, or by the L-shaped composite insulator spacer, while the same implantation procedure allows a shallower, heavily doped N type source/drain region to be formed in an area of the P type semiconductor substrate not covered by the gate structure or by the vertical feature of the composite insulator spacer. An anneal procedure is next used to activate the implanted dopants, followed by formation of a self aligned metal silicide (salicide), layer, on the top surface of the gate structures as well as on the exposed portions of both heavily doped source/drain regions.